
`timescale 1ns / 1ps

`define RISCV_PRIV_MODE_U   0
`define RISCV_PRIV_MODE_S   1
`define RISCV_PRIV_MODE_M   3

`define AXI_ADDR_WIDTH      64
`define AXI_DATA_WIDTH      64
`define AXI_ID_WIDTH        4
`define AXI_USER_WIDTH      1

`define ZERO_WORD           64'h00000000_00000000   
`define DOUBLE_REG_BUS      127:0
`define REG_BUS              63:0     

`define ALU_SEL_BUS         3:0
`define ALU_SEL_WIDTH       4

`define ALU_SEL_OR          4'b0001
`define ALU_SEL_AND         4'b0010
`define ALU_SEL_XOR         4'b0011
`define ALU_SEL_SLL         4'b0100
`define ALU_SEL_SRL         4'b0101
`define ALU_SEL_SRA         4'b0110
`define ALU_SEL_SLT         4'b0111
`define ALU_SEL_ADD         4'b1000
`define ALU_SEL_SUB         4'b1001

`define TRANSFER_SEL_BUS    2:0
`define TRANSFER_SEL_WIDTH  3

`define TRANSFER_JAL        3'b000
`define TRANSFER_JALR       3'b001
`define TRANSFER_BEQ        3'b010
`define TRANSFER_BNE        3'b011
`define TRANSFER_BLT        3'b100
`define TRANSFER_BGE        3'b101
`define TRANSFER_BLTU       3'b110
`define TRANSFER_BGEU       3'b111

`define MEM_SEL_BUS         3:0
`define MEM_SEL_WIDTH       4

`define MEM_LB              4'b0000
`define MEM_LH              4'b0001
`define MEM_LW              4'b0010
`define MEM_LD              4'b0011
`define MEM_LBU             4'b0100
`define MEM_LHU             4'b0101
`define MEM_LWU             4'b0110
`define MEM_SB              4'b1000
`define MEM_SH              4'b1001
`define MEM_SW              4'b1010
`define MEM_SD              4'b1011

`define CSR_SEL_BUS         1:0
`define CSR_SEL_WIDTH       2

`define CSR_CSRRW           2'b01
`define CSR_CSRRS           2'b10
`define CSR_CSRRC           2'b11


`define RD_SEL_BUS          1:0
`define RD_SEL_WIDTH        2

`define RD_SEL_ALU          2'b00
`define RD_SEL_LINK         2'b01
`define RD_SEL_CSR          2'b10
`define RD_SEL_LOAD         2'b11

`define INST_ADD        8'b0001_0000
`define INST_SUB        8'b0001_0001
`define INST_SLT        8'b0001_0010
`define INST_SLTU       8'b0001_0011

`define INST_ADDW       8'b0001_1000
`define INST_SUBW       8'b0001_1001

`define INST_XOR        8'h21
`define INST_AND        8'h22
`define INST_OR         8'h23

`define INST_SLL        8'b0011_0000
`define INST_SRL        8'b0011_0001
`define INST_SRA        8'b0011_0010

`define INST_SLLW       8'b0011_1000
`define INST_SRLW       8'b0011_1001
`define INST_SRAW       8'b0011_1010
//8'h4?
`define INST_LB         8'b0100_000_1
`define INST_LBU        8'b0100_000_0
`define INST_LH         8'b0100_001_1
`define INST_LHU        8'b0100_001_0
`define INST_LW         8'b0100_010_1
`define INST_LWU        8'b0100_010_0
`define INST_LD         8'b0100_011_1

`define INST_SB         8'b0100_100_1
`define INST_SH         8'b0100_101_1
`define INST_SW         8'b0100_110_1
`define INST_SD         8'b0100_111_1

`define INST_LUI        8'h61

`define INST_AUIPC      8'h71

`define INST_JAL        8'h81
`define INST_JALR       8'h82

`define INST_BEQ        8'h91
`define INST_BNE        8'h92
`define INST_BLT        8'h93
`define INST_BGE        8'h94
`define INST_BLTU       8'h95
`define INST_BGEU       8'h96

`define INST_ECALL      8'ha0
`define INST_MRET       8'ha4
`define INST_CSRRW      8'ha1
`define INST_CSRRS      8'ha2
`define INST_CSRRC      8'ha3

`define CSR_MCYCLE      12'hb00
`define CSR_MSTATUS     12'h300
`define CSR_MTVEC       12'h305
`define CSR_MEPC        12'h341
`define CSR_MCAUSE      12'h342
`define CSR_MIE         12'h304
`define CSR_MIP         12'h344
`define CSR_MSCRATCH    12'h340